1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to techniques for improving performance of the semiconductor integrated circuit.
2. Description of the Background Art
With rapid advancement of techniques for manufacturing a semiconductor device, great improvement in performance of a microprocessor has been achieved. On the other hand, memory integration has been improved, but access performance has not been so much enhanced. For this reason, the difference in performance between a microprocessor and a memory is becoming wider and therefore it becomes hard to achieve so much improvement in performance of a system on the whole even if it carries a high-performance microprocessor. For the microprocessor always performs a transfer of data with the memory and a time-consuming memory access hinders an efficient internal processing of the microprocessor. Then, there arises a need to suppress degradation in performance due to memory access and enhance the performance of the system on the whole.
FIG. 29 shows a prior art semiconductor integrated circuit, which is configured so as to eliminate the difference in performance between a microprocessor and a memory. In FIG. 29, reference numerals 1, 2 and 3 designate a memory, a microprocessor and a bus controller, respectively. The bus controller 3 internally has a control unit 4 and a register 5. This figure shows an exemplary configuration to achieve an improvement in efficiency of data transfer when an internal bus of the microprocessor 2 and an external bus (e.g., address bus, data bus) have different bus widths. For example, it is now assumed that a wider bus has a 16-bit width and a narrower bus has an 8-bit width. When a data transfer is performed from the narrower bus to the wider bus, 8-bit data from the narrower bus are first stored in the register 5 and another 8-bit data from the narrower bus are received to make 16-bit data, and then the 16-bit data are transmitted to the wider bus. When a data transfer is performed from the wider bus to the narrower bus, 16-bit data from the wider bus arc divided into two 8-bit data and stored into the register 5, and then each 8-bit data arc transmitted to the narrower bus.
Thus, in the prior art semiconductor integrated circuit, since the bus controller operates independently from the microprocessor, it is impossible to exercise a register control taking the internal processing of the microprocessor into account. That causes degradation in performance of the semiconductor integrated circuit. For example, it is impossible to clear the data stored in the register or perform such an internal processing as not to fill the register with data during a load delay when, for example, a branch instruction is executed or a branch is taken. Furthermore, it is difficult for the microprocessor to internally perform a dynamic scheduling by capturing in advance a plurality of instructions therein. The dynamic scheduling means herein changing of the executing order of instructions stored in a queue, by which improvement in performance may be expected with no trouble.
Moreover, in the prior art semiconductor integrated circuit, providing a control function over data division and the like outside the microprocessor causes an increase in the number of components of the semiconductor integrated circuit and an increase in manufacturing cost.